The present invention relates to a semiconductor device including a gate insulation film of a high dielectric constant material, and a method for fabricating the semiconductor device.
With the recent progress of the technique for increasing the integration and speed-up of semiconductor devices, MOSFET is increasingly nanonized. As the gate insulation film is increasingly thinned with the increasing nanonization, a problem of increased gate leak current, etc. due to tunnel current, etc. become conspicuous.
To suppress this problem, various trials are made to realize a capacitance equivalent oxide thickness (CET), which is small but ensures a physical film thickness, by using the gate insulation film of a high dielectric constant material, such as HfO2, Ta2O5, etc. (hereinafter called “the High-k gate insulation film”).
The Patent Reference 1 is Specification of Japanese Patent Application Unexamined Publication No. 2003-303820.
However, when the gate insulation film is formed of the High-k gate insulation film, and a gate electrode of, e.g., polysilicon is formed on the gate insulation film, a problem is that the threshold voltage of the transistor is shifted from a design value.